Dublin Core
Title
FPGA-based Implementation of IIR Filter for Real-Time Noise Reduction in Signal
Abstract
Filtering of unwanted frequencies represents the main aspect of digital signal processing (DSP) in
any modern communication system. The main role of the filter is to perform attenuation of certain frequencies
and pass only frequencies of interest. In a DSP system, sampled or discrete-time signals are processed by digital
filters using different mathematical operations. Digital filters are commonly categorized as Finite Impulse
Response (FIR) and Infinite Impulse Response (IIR). This research focuses on the full VHDL implementation
of digital second-order lowpass IIR filter for reducing the noisy frequencies on the FPGA board. The initial
step is to determine, from continuous time domain function, the transfer function in the complex {s} domain,
then map transfer function in complex {z} domain and finally calculate the difference equation in discrete-time
domain of the system with adequate coefficients. Prior to the FPGA implementation, the IIR filter is tested in
MATLAB using a signal with mixed frequencies and signal with randomly generated noise. The digital
implementation is completed by using fixed-point binary vectors and clocked processes.
any modern communication system. The main role of the filter is to perform attenuation of certain frequencies
and pass only frequencies of interest. In a DSP system, sampled or discrete-time signals are processed by digital
filters using different mathematical operations. Digital filters are commonly categorized as Finite Impulse
Response (FIR) and Infinite Impulse Response (IIR). This research focuses on the full VHDL implementation
of digital second-order lowpass IIR filter for reducing the noisy frequencies on the FPGA board. The initial
step is to determine, from continuous time domain function, the transfer function in the complex {s} domain,
then map transfer function in complex {z} domain and finally calculate the difference equation in discrete-time
domain of the system with adequate coefficients. Prior to the FPGA implementation, the IIR filter is tested in
MATLAB using a signal with mixed frequencies and signal with randomly generated noise. The digital
implementation is completed by using fixed-point binary vectors and clocked processes.
Keywords
digital signal processing; IIR filter; digital design; FPGA; VHDL; Bode diagram
Identifier
2637-2835
DOI
10.14706/JONSAE2021316